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| 19-2862; Rev 1; 2/05 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux General Description The MAX9765/MAX9766/MAX9767 family combines speaker, headphone, and microphone amplifiers, all in a small thin QFN package. The MAX9765 is targeted at stereo speaker playback applications and includes a stereo bridge-tied load (BTL) speaker amp, stereo headphone amp, single-ended output mic amp, input MUX, and I 2C control. The MAX9766 is targeted at mono speaker playback applications and includes a mono BTL speaker amp, stereo headphone amp, differential output mic amp, input MUX, and I2C control. The MAX9767 is targeted at applications that do not require a headphone amp and includes a stereo BTL speaker amp, differential output mic amp, and parallel control. These devices operate from a single 2.7V to 5.5V supply. A high 95dB PSRR allows these devices to operate from noisy supplies without additional power conditioning. An ultra-low 0.003% THD+N ensures clean, low distortion amplification of the audio signal. Patented click-and-pop suppression eliminates audible transients on power and shutdown cycles. In speaker mode, the amplifiers can deliver up to 750mW of continuous average power into a 4 load. In headphone mode, the amplifier can deliver up to 65mW of continuous average power into a 16 load. The gain of the amplifiers is externally set, allowing maximum flexibility in optimizing output levels for a given load. The MAX9765/MAX9766 also feature a 2:1 input multiplexer, allowing multiple audio sources to be selected. The various functions are controlled by either an I 2Ccompatible (MAX9765/MAX9766) or simple parallel control interface (MAX9767). All devices include two low-noise microphone preamps, a differential amp for internal microphones, and a single-ended amplifier for additional external microphones. A microphone bias output is provided, reducing external component count. The MAX9765/MAX9766/MAX9767 are available in a thermally efficient 32-pin thin QFN package (5mm 5mm 0.8mm). All devices have short-circuit and thermal-overload protection (OVP) and are specified over the extended -40C to +85C temperature range. Features 750mW BTL Stereo Speaker Amplifier 65mW Stereo Headphone Amplifier 2.7V to 5.5V Single-Supply Operation Patented Click-and-Pop Suppression Low 0.003% THD+N Low Quiescent Current: 13mA Low-Power Shutdown Mode: 5A MUTE Function Headphone Sense Input Stereo 2:1 Input Multiplexer Optional 2-Wire, I2C-Compatible, or Parallel Interface Small 32-Pin Thin QFN (5mm 5mm 0.8mm) Package MAX9765/MAX9766/MAX9767 Ordering Information PART MAX9765ETJ MAX9766ETJ MAX9767ETJ TEMP RANGE -40oC to +85oC -40oC to +85oC -40oC to +85oC PIN-PACKAGE 32 Thin QFN-EP* 32 Thin QFN-EP* 32 Thin QFN-EP* *EP = Exposed paddle. Pin Configurations and Functional Diagrams appear at end of data sheet. Simplified Diagram MUX INL1 INL2 MUX INR1 INR2 SPKR RIGHT DEVICE CONTROL SPKR LEFT HEADPHONE Applications PDA Audio Systems Tablet PCs Cell Phones Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification defined by Philips. CONTROL Notebooks Digital Cameras MICINMICIN+ AUXIN MICBIAS BIAS MUX MICOUT MAX9765 ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................................+6V SVDD to GND .........................................................................+6V SVDD to VDD .........................................................................-0.3V PVDD to VDD .......................................................................0.3V PGND to GND.....................................................................0.3V All Other Pins to GND.................................-0.3V to (VDD + 0.3V) Output Short-Circuit Duration (to VDD or GND)..........Continuous Continuous Input Current (into any pin except power-supply and output pins) ...............................................................20mA Continuous Power Dissipation (TA = +70C) 32-Pin Thin QFN (derate 26.3mW/C above +70C) ...2105.3mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = PVDD = 3.0V, GND = 0, HPS = MUTE = GND, SHDN = 3V, CBIAS = 1F, RIN = RF = 15k, RL = . TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER Supply Voltage Range Quiescent Supply Current (IVDD + IPVDD) Shutdown Current Switching Time Turn-On/Turn-Off Time Input Bias Current Thermal Shutdown Threshold Thermal Shutdown Hysteresis Output Short-Circuit Current STANDBY SUPPLY (SVDD) Standby Current ISVDD VBIAS = 1.25V, VDD = 0V VBIAS = 1.5V, VDD = 3V VOUT_+ - VOUT_-, AV = 1V/V VDD = 2.7V to 5.5V f = 1kHz, VRIPPLE = 200mVP-P fIN = 1kHz, THD+N = 1%, TA = +25oC (Note 2) fIN = 1kHz, BW = 22Hz to 22kHz RL = 8 RL = 4 POUT = 200mW, RL = 8 POUT = 400mW, RL = 4 400 72 10 85 72 450 750 0.033 % 0.065 89 dB 230 400 5 45 A To VDD or GND SYMBOL VDD/PVDD IDD ISHDN tSW tON/OFF IBIAS CONDITIONS Inferred from PSRR test Speaker mode MAX9765/MAX9767 MAX9766 MIN 2.7 12 7 7 5 10 250 25 50 150 8 1.2 TYP MAX 5.5 28 17 17 18 A s ms nA o o UNITS V mA Headphone mode, HPS = VDD SHDN = GND Gain or input switching (MAX9765/MAX9766) CBIAS = 1F, settled to 90% CBIAS = 0.1F, settled to 90% C C A OUTPUT AMPLIFIERS (SPEAKER MODE) Output Offset Voltage Power-Supply Rejection Ratio Output Power VOS PSRR POUT mV dB mW Total Harmonic Distortion Plus Noise THD+N Signal-to-Noise Ratio SNR RL = 8, VOUT_ = 1.4VRMS, BW = 22Hz to 22kHz 2 _______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux ELECTRICAL CHARACTERISTICS (continued) (VDD = PVDD = 3.0V, GND = 0, HPS = MUTE = GND, SHDN = 3V, CBIAS = 1F, RIN = RF = 15k, RL = . TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER Maximum Capacitive Load Drive Slew Rate Crosstalk OUTPUT AMPLIFIERS (HEADPHONE MODE) VDD = 2.7V to 5.5V Power-Supply Rejection Ratio PSRR f = 1kHz, VRIPPLE = 200mVP-P f = 20kHz, VRIPPLE = 200mVP-P Output Power POUT fIN = 1kHz, THD+N = 1%, TA = +25oC (Note 2) RL = 32 RL = 16 VOUT = 0.7RMS, RL = 10k Total Harmonic Distortion Plus Noise THD+N fIN = 1kHz, BW = 22Hz to 22kHz POUT = 15mW, RL = 32 POUT = 30mW, RL = 16 Signal-to-Noise Ratio Slew Rate Maximum Capacitive Load Drive Crosstalk BIAS VOLTAGE (BIAS) BIAS Voltage Output Resistance VBIAS RBIAS VDD - VOH VOL - GND VDD - VOH VOL - GND 1.4 1.5 50 35 50 80 70 0.6 10 50 2 31 11.6 0.01 300 100 5 70 400 150 400 V/s mA pF mV nV/Hz % kHz k mV 1.6 V k SNR SR CL No sustained oscillations fIN = 10kHz RL = 8, VOUT_ = 1.4VRMS, BW = 20Hz to 22kHz 35 95 75 50 40 65 0.002 0.005 0.004 89 0.7 200 79 dB V/s pF dB % mW dB SYMBOL CL SR fIN = 10kHz CONDITIONS No sustained oscillations MIN TYP 400 1.4 73 MAX UNITS pF V/s dB MAX9765/MAX9766/MAX9767 MICROPHONE AMPLIFIER GENERAL RL = 100k Output Voltage Swing VOUT RL = 2k Slew Rate Output Short-Circuit Current Maximum Capacitive Load Drive Input Offset Voltage Input Noise-Voltage Density Total Harmonic Distortion Plus Noise Small-Signal Bandwidth Input Resistance CL VOS eN THD+N BW-3dB RIN fIN = 1kHz AV = 20dB AV = 40dB SR AV = 10dB To VDD or GND No sustained oscillations DIFFERENTIAL INPUT AMPLIFIER (MICIN+, MICIN-) VDD = 3V, VOUT = 0.35VRMS, AV = 10dB, fIN = 1kHz, BW = 22Hz to 22kHz AV = 40dB, VOUT = 100mVP-P MICIN_ to GND _______________________________________________________________________________________ 3 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 ELECTRICAL CHARACTERISTICS (continued) (VDD = PVDD = 3.0V, GND = 0, HPS = MUTE = GND, SHDN = 3V, CBIAS = 1F, RIN = RF = 15k, RL = . TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER Input Resistance Matching Differential Gain Accuracy SYMBOL RMATCH MAX9765, AV = 4dB to 39dB AVDIFF MAX9766, AV = 10dB to 45dB MAX9767, AV = 10dB, 20dB, 30dB Common-Mode Rejection Ratio CMRR AV = 10dB, fIN = 1kHz, VCM = 200mVP-P, RS = 2k VDD = 2.7V to 5.5V Power-Supply Rejection Ratio PSRR AV = 10dB, output referred f = 1kHz, VRIPPLE = 200mVP-P f = 20kHz, VRIPPLE = 200mVP-P Common-Mode Input Voltage Range Input Offset Voltage Input Noise-Voltage Density Total Harmonic Distortion Plus Noise Small-Signal Bandwidth Input Resistance Voltage Gain Accuracy VCM 62 CONDITIONS MIN TYP 1 2 2 2 60 80 80 68 1 V dB 4 4 4 dB % MAX UNITS % SINGLE-ENDED INPUT AMPLIFIER (AUXIN) VOS eN THD+N BW-3dB RIN AV VDD = 2.7V to 5.5V Power-Supply Rejection Ratio PSRR AV = 10dB, output referred f = 1kHz, VRIPPLE = 200mVP-P f = 20kHz, VRIPPLE = 200mVP-P MICROPHONE BIAS OUTPUT (MICBIAS) Microphone Bias Output Voltage Output Noise-Voltage Density Power-Supply Rejection Ratio VMICBIAS eN PSRR VDD = 2.7V to 5.5V, ILOAD = 500A f = 1kHz VDD = 2.7V to 5.5V fIN = 1kHz, VRIPPLE = 200mVP-P 2 0.8 1 VDD GND FLOAT 63 2.4 2.5 52 72 70 2.6 V nV/Hz dB 65 AV = 20dB, fIN = 1kHz AV = 10dB, fIN = 1kHz, BW = 22Hz to 22kHz, VOUT = 0.7VRMS AV = 20dB, VOUT = 100mVP-P 4 73 0.01 200 100 4 80 76 58 dB 10 mV nV/Hz % kHz k % DIGITAL INPUTS (MUTE, SHDN, INT/EXT) Input Voltage High Input Voltage Low Input Leakage Current Input Voltage High Input Voltage Low Input Voltage Mid VIH VIL IIN VIH VIL VIZ V V A V V V MAX9767 MICGAIN INPUT (TRI-STATE PIN)) 4 _______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux ELECTRICAL CHARACTERISTICS (continued) (VDD = PVDD = 3.0V, GND = 0, HPS = MUTE = GND, SHDN = 3V, CBIAS = 1F, RIN = RF = 15k, RL = . TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER HEADPHONE SENSE INPUT (HPS) Input Voltage High Input Voltage Low Input Leakage Current VIH VIL IIN VDD > 3.6V VDD 3.6V 3 2 0.8 0.2 IIH IIL CIN VOL IOH fSCL tBUF tHD:STA tSU:STA tLOW tHIGH tSU:DAT tHD:DAT tR tF tF tSP (Note 3) (Note 4) (Note 4) (Note 4) (Note 5) 1.3 0.6 0.6 1.3 0.6 100 0 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 50 0.9 300 300 250 IOL = 3mA VOH = 3V VIN = 3V VIN = 0V 10 0.4 1 400 1 1 0.9 x VDD 0.7 x VDD 1 V V A SYMBOL CONDITIONS MIN TYP MAX UNITS MAX9765/MAX9766/MAX9767 2-WIRE SERIAL INTERFACE (SCL, SDA, ADD) (MAX9765/MAX9766) Input Voltage High Input Voltage Low Input Hysteresis Input High Leakage Current Input Low Leakage Current Input Capacitance Output Voltage Low Output Current High Serial Clock Frequency Bus Free Time Between STOP and START Conditions START Condition Hold Time START Condition Setup Time Clock Period Low Clock Period High Data Setup Time Data Hold Time Receive SCL/SDA Rise Time Receive SCL/SDA Fall Time Transmit SDA Fall Time Pulse Width of Suppressed Spike VIH VIL V V V A A pF V A kHz s s s s s ns s ns ns ns ns TIMING CHARACTERISTICS (MAX9765/MAX9766) All devices are 100% production tested at +25C. All temperature limits are guaranteed by design. POUT limits are tested by a combination of electrical and guaranteed by design. A device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL's falling edge. CB = total capacitance of one of the bus lines in picofarads. Device tested with CB = 400pF. 1k pullup resistors connected from SDA/SCL to VDD. Note 5: Input filters on SDA, SCL, and ADD suppress noise spikes less than 50ns. Note 1: Note 2: Note 3: Note 4: _______________________________________________________________________________________ 5 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 Typical Operating Characteristics (VDD = PVDD = 5V, BW = 22Hz to 22kHz, TA = +25C, unless otherwise noted.) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SPEAKER MODE) MAX9765 toc02 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SPEAKER MODE) MAX9765 toc01 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SPEAKER MODE) MAX9765 toc03 1 1 1 POUT = 100mW 0.1 THD+N (%) POUT = 250mW 0.1 THD+N (%) POUT = 100mW POUT = 250mW POUT = 100mW 0.1 THD+N (%) POUT = 250mW POUT = 500mW 0.01 VDD = 5V RL = 4 AV = 2V/V 0.001 10 100 1k FREQUENCY (Hz) 10k 100k POUT = 500mW 0.01 VDD = 5V RL = 4 AV = 4V/V 0.001 10 100 1k FREQUENCY (Hz) 10k 100k POUT = 500mW 0.01 VDD = 3V RL = 4 AV = 2V/V 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SPEAKER MODE) MAX9765 toc04 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SPEAKER MODE) MAX9765 toc05 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SPEAKER MODE) MAX9765 toc06 1 1 1 POUT = 100mW 0.1 THD+N (%) POUT = 250mW 0.1 THD+N (%) POUT = 300mW POUT = 50mW THD+N (%) 0.1 POUT = 300mW POUT = 50mW POUT = 500mW 0.01 VDD = 3V RL = 4 AV = 4V/V 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.01 POUT = 150mW VDD = 5V RL = 8 AV = 2V/V 0.01 POUT = 150mW VDD = 5V RL = 8 AV = 4V/V 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 10 100 1k FREQUENCY (Hz) 10k 100k TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SPEAKER MODE) MAX9765 toc07 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SPEAKER MODE) MAX9765 toc08 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER MODE) VDD = 5V RL = 4 AV = 2V/V MAX9765 toc09 1 1 100 f = 1kHz 10 0.1 THD+N (%) POUT = 300mW POUT = 50mW 0.1 THD+N (%) POUT = 150mW POUT = 50mW THD+N (%) 1 f = 10kHz 0.1 0.01 POUT = 150mW VDD = 3V RL = 8 AV = 4V/V 0.01 POUT = 300mW VDD = 3V RL = 8 AV = 4V/V 0.01 f = 20Hz 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 0 0.25 0.50 0.75 1.00 1.25 OUTPUT POWER (W) 6 _______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux Typical Operating Characteristics (continued) (VDD = PVDD = 5V, BW = 22Hz to 22kHz, TA = +25C, unless otherwise noted.) MAX9765/MAX9766/MAX9767 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER MODE) MAX9765 toc10 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER MODE) MAX9765 toc11 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER MODE) VDD = 3V RL = 4 AV = 4V/V f = 1kHz MAX9765 toc12 100 VDD = 5V RL =4 AV = 4V/V f = 1kHz 100 VDD = 3V RL = 4 AV = 2V/V f = 1kHz 100 10 10 10 THD+N (%) THD+N (%) THD+N (%) 1 f = 10kHz 0.1 1 f = 10kHz 0.1 1 f = 10kHz 0.1 0.01 f = 20Hz 0.001 0 0.2 0.4 OUTPUT POWER (W) 0.6 0.8 0.01 f = 20Hz 0.01 f = 20Hz 0.001 0 0.25 0.50 0.75 1.00 OUTPUT POWER (W) 0.001 0 0.25 0.50 0.75 1.00 OUTPUT POWER (W) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER MODE) MAX9765 toc13 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER MODE) MAX9765 toc14 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER MODE) VDD = 3V RL = 8 AV = 2V/V MAX9765 toc15 100 VDD = 5V RL = 8 AV = 2V/V f = 1kHz 100 VDD = 5V RL = 8 AV = 4V/V f = 1kHz 100 f = 1kHz 10 10 10 THD+N (%) THD+N (%) THD+N (%) 1 f = 10kHz 0.1 1 f = 10kHz 0.1 1 f = 10kHz 0.1 0.01 f = 20Hz 0.001 0 0.2 0.4 OUTPUT POWER (W) 0.6 0.8 0.01 f = 20Hz 0.001 0 0.2 0.4 OUTPUT POWER (W) 0.6 0.8 0.01 f = 20Hz 0.001 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 OUTPUT POWER (W) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER MODE) MAX9765 toc16 OUTPUT POWER vs. LOAD RESISTANCE (SPEAKER MODE) MAX9765 toc17 OUTPUT POWER vs. LOAD RESISTANCE (SPEAKER MODE) 900 800 OUTPUT POWER (mW) 700 600 500 400 300 200 100 THD+N = 1% THD+N = 10% VCC = 3V MAX9765 toc18 100 VDD = 3V RL = 8 AV = 4V/V f = 1kHz 1200 VCC = 5V 1000 OUTPUT POWER (mW) 800 600 400 THD+N = 1% 200 0 THD+N = 10% 1000 10 THD+N (%) 1 f = 10kHz 0.1 0.01 f = 20Hz 0.001 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 OUTPUT POWER (W) 0 0 10 100 1k 10k 0 10 100 1k 10k LOAD RESISTANCE () LOAD RESISTANCE () _______________________________________________________________________________________ 7 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 Typical Operating Characteristics (continued) (VDD = PVDD = 5V, BW = 22Hz to 22kHz, TA = +25C, unless otherwise noted.) POWER DISSIPATION vs. OUTPUT POWER (SPEAKER MODE) MAX9765 toc19 POWER DISSIPATION vs. OUTPUT POWER (SPEAKER MODE) MAX9765 toc20 POWER DISSIPATION vs. OUTPUT POWER (SPEAKER MODE) MAX9765 toc21 1.6 1.4 POWER DISSIPATION (W) 1.2 1.0 0.8 0.6 0.4 0.2 0 0 0.25 0.50 0.75 VDD = 5V RL = 4 f = 1kHz 0.9 0.8 POWER DISSIPATION (W) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.15 0.30 0.45 VDD = 5V RL = 8 f = 1kHz 0.60 0.6 0.5 POWER DISSIPATION (W) 0.4 0.3 0.2 0.1 0 VDD = 3V RL = 4 f = 1kHz 0 0.25 0.50 0.75 1.00 0.75 1.00 OUTPUT POWER (W) OUTPUT POWER (W) OUTPUT POWER (W) POWER DISSIPATION vs. OUTPUT POWER (SPEAKER MODE) MAX9765 toc22 OUTPUT POWER vs. TEMPERATURE (SPEAKER MODE) MAX9765 toc23 OUTPUT POWER vs. TEMPERATURE (SPEAKER MODE) 700 OUTPUT POWER (mW) 600 500 THD+N = 1% 400 300 200 MAX9765 toc24 0.30 0.25 POWER DISSIPATION (W) 0.20 0.15 0.10 0.05 0 0 0.15 0.30 0.45 VDD = 3V RL = 8 f = 1kHz 1200 1000 THD+N = 10% OUTPUT POWER (mW) 800 600 400 200 0 THD+N = 1% 800 THD+N = 10% f = 1kHz RL = 4 -40 -15 10 35 60 85 100 0 -40 TEMPERATURE (C) f = 1kHz RL = 8 -15 10 35 60 85 0.60 OUTPUT POWER (W) TEMPERATURE (C) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (SPEAKER MODE) MAX9765 toc25 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (SPEAKER MODE) -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 OUT_+ OUT_100mV/div 10 100 1k FREQUENCY (Hz) 10k 100k OUT_+ AND OUT_500mV/div VDD = 3V MAX9765 toc26 ENTERING SHUTDOWN (SPEAKER MODE) MAX9765 toc27 0 -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 10 100 1k FREQUENCY (Hz) 10k VDD = 5V 0 SHDN 2V/div 100k 200ms/div RL = 8 INPUT AC-COUPLED TO GND 8 _______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux Typical Operating Characteristics (continued) (VDD = PVDD = 5V, BW = 22Hz to 22kHz, TA = +25C, unless otherwise noted.) EXITING SHUTDOWN (SPEAKER MODE) MAX9765 toc28 MAX9765/MAX9766/MAX9767 ENTERING POWER-DOWN (SPEAKER MODE) MAX9765 toc29 SHDN VCC 2V/div 2V/div OUT_+ AND OUT_500mV/div OUT_+ AND OUT 500mV/div OUT_+ - OUT 100mV/div OUT_+ OUT_100mV/div 200ms/div RL = 8 INPUT AC-COUPLED TO GND 200ms/div RL = 8 INPUT AC-COUPLED TO GND CBIAS = 1F POWER-UP (SPEAKER MODE) MAX9765 toc30 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (HEADPHONE MODE) VDD = 5V RL = 16 AV = 1V/V 0.1 THD+N (%) MAX9765 toc31 1 2V/div VCC 500mV/div OUT_+ AND OUT 100mV/div POUT = 10mW 0.01 POUT = 25mW OUT_+ - OUT 0.001 200ms/div RL = 8 INPUT AC-COUPLED TO GND CBIAS = 1F 10 100 1k POUT = 50mW 10k 100k FREQUENCY (Hz) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (HEADPHONE MODE) MAX9765 toc32 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (HEADPHONE MODE) MAX9765 toc33 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (HEADPHONE MODE) VDD = 3V RL = 16 AV = 2V/V 0.1 THD+N (%) POUT = 25mW 0.01 POUT = 10mW MAX9765 toc34 1 VDD = 5V RL = 16 AV = 2V/V 0.1 THD+N (%) POUT = 50mW 0.01 1 VDD = 3V RL = 16 AV = 1V/V 0.1 THD+N (%) 1 POUT = 25mW POUT = 25mW 0.01 POUT = 50mW POUT = 10mW 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 10 100 1k POUT = 10mW 0.001 10k 100k 10 100 1k POUT = 50mW 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) _______________________________________________________________________________________ 9 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 Typical Operating Characteristics (continued) (VDD = PVDD = 5V, BW = 22Hz to 22kHz, TA = +25C, unless otherwise noted.) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (HEADPHONE MODE) MAX9765 toc35 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (HEADPHONE MODE) MAX9765 toc36 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (HEADPHONE MODE) VDD = 3V RL = 32 AV = 1V/V 0.1 THD+N (%) MAX9765 toc37 1 VDD = 5V RL = 32 AV = 1V/V 0.1 THD+N (%) 1 VDD = 5V RL = 32 AV = 2V/V 0.1 THD+N (%) POUT = 10mW 0.01 POUT = 5mW 1 POUT = 10mW 0.01 POUT = 5mW POUT = 10mW 0.01 POUT = 5mW 0.001 10 100 1k POUT = 20mW 10k 100k POUT = 20mW 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 10 100 1k POUT = 20mW 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (HEADPHONE MODE) MAX9765 toc38 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (HEADPHONE MODE) MAX9765 toc39 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (HEADPHONE MODE) VDD = 5V RL = 16 AV = 2V/V f = 1kHz MAX9765 toc40 1 VDD = 3V RL = 32 AV = 2V/V 0.1 THD+N (%) POUT = 10mW 0.01 POUT = 5mW 100 VDD = 5V RL = 16 AV = 1V/V f = 1kHz 100 10 THD+N (%) 10 1 f = 20Hz 0.1 f = 10kHz 0.01 THD+N (%) 1 f = 20Hz 0.1 f = 10kHz 0.01 POUT = 20mW 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 0 20 40 60 80 100 120 OUTPUT POWER (mW) 0.001 0 20 40 60 80 100 120 OUTPUT POWER (mW) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (HEADPHONE MODE) MAX9765 toc41 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (HEADPHONE MODE) MAX9765 toc42 OUTPUT POWER vs. LOAD RESISTANCE (HEADPHONE MODE) VCC = 5V 140 OUTPUT POWER (mW) 120 100 80 60 THD+N = 1% 40 20 THD+N = 10% MAX9765 toc43 100 VDD = 3V RL = 16 AV = 1V/V f = 1kHz 100 VDD = 3V RL = 16 AV = 2V/V f = 1kHz 160 10 10 THD+N (%) THD+N (%) 1 f = 20Hz f = 10kHz 1 f = 20Hz 0.1 f = 10kHz 0.1 0.01 0.01 0.001 0 20 40 60 80 100 120 OUTPUT POWER (mW) 0.001 0 20 40 60 80 100 120 OUTPUT POWER (mW) 0 1 10 100 1k 10k LOAD RESISTANCE () 10 ______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux Typical Operating Characteristics (continued) (VDD = PVDD = 5V, BW = 22Hz to 22kHz, TA = +25C, unless otherwise noted.) OUTPUT POWER vs. LOAD RESISTANCE (HEADPHONE MODE) MAX9765 toc44 MAX9765/MAX9766/MAX9767 POWER DISSIPATION vs. OUTPUT POWER (HEADPHONE MODE) MAX9765 toc45 POWER DISSIPATION vs. OUTPUT POWER (HEADPHONE MODE) RL = 16 MAX9765 toc46 140 VCC = 3V 120 OUTPUT POWER (mW) 100 80 60 40 20 0 1 10 100 1k THD+N = 1% THD+ N = 10% 140 120 POWER DISSIPATION (mW) 100 80 60 40 20 0 VDD = 5V f = 1kHz 0 25 50 75 RL = 32 RL = 16 60 50 POWER DISSIPATION (mW) 40 RL = 32 30 20 10 0 VDD = 3V f = 1kHz 0 15 30 45 60 75 10k 100 LOAD RESISTANCE () OUTPUT POWER (mW) OUTPUT POWER (mW) OUTPUT POWER vs. TEMPERATURE (HEADPHONE MODE) MAX9765 toc47 OUTPUT POWER vs. TEMPERATURE (HEADPHONE MODE) MAX9765 toc48 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (HEADPHONE MODE) -10 -20 -30 PSRR (dB) VDD = 5V MAX9765 toc49 100 THD+N = 10% 80 OUTPUT POWER (mW) THD+N = 1% 60 60 50 OUTPUT POWER (mW) 40 30 20 10 0 THD+N = 10% 0 THD+N = 1% -40 -50 -60 -70 -80 40 20 f = 1kHz RL = 16 0 -40 -15 10 35 60 85 TEMPERATURE (C) f = 1kHz RL = 32 -40 -15 10 35 60 85 -90 -100 10 100 1k FREQUENCY (Hz) 10k 100k TEMPERATURE (C) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (HEADPHONE MODE) -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 10 100 1k FREQUENCY (Hz) 10k 100k VDD = 3V MAX9765 toc50 ENTERING SHUTDOWN (HEADPHONE MODE) MAX9765 toc51 EXITING SHUTDOWN (HEADPHONE MODE) MAX9765 toc52 0 SHDN 2V/div SHDN 2V/div OUT_+ 500mV/div HP JACK 100mV/div 200ms/div RL = 16 INPUT AC-COUPLED TO GND OUT_+ 500mV/div HP JACK 100mV/div 200ms/div RL = 16 INPUT AC-COUPLED TO GND ______________________________________________________________________________________ 11 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 Typical Operating Characteristics (continued) (VDD = PVDD = 5V, BW = 22Hz to 22kHz, TA = +25C, unless otherwise noted.) ENTERING POWER-DOWN (HEADPHONE MODE) MAX9765 toc53 EXITING POWER-DOWN (HEADPHONE MODE) MAX9765 toc54 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DIFFERENTIAL INPUT) VDD = 5V MAX9765 toc55 1 VCC 2V/div VCC 2V/div 0.1 OUT_+ 500mV/div THD+N (%) OUT_+ 500mV/div VOUT = 0.26VRMS 0.01 HP JACK 100mV/div 200ms/div RL = 16 INPUT AC-COUPLED TO GND HP JACK 100mV/div 0.001 200ms/div RL = 16 INPUT AC-COUPLED TO GND 10 100 VOUT = 0.35VRMS 1k FREQUENCY (Hz) 10k 100k TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DIFFERENTIAL INPUT) MAX9765 toc56 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT AMPLITUDE (DIFFERENTIAL INPUT) MAX9765 toc57 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT AMPLITUDE (DIFFERENTIAL INPUT) VDD = 3V 10 f = 1kHz MAX9765 toc58 1 VDD = 3V 100 VDD = 5V 10 f = 1kHz 100 THD+N (%) THD+N (%) THD+N (%) 0.1 VOUT = 0.26VRMS 1 1 f = 10kHz 0.1 0.1 0.01 VOUT = 0.35VRMS 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.01 f = 10kHz 0.01 f = 100Hz f = 100Hz 0.001 0 1 2 3 0 1 2 3 OUTPUT VOLTAGE (VRMS) OUTPUT VOLTAGE (VRMS) 0.001 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DIFFERENTIAL INPUT) MAX9765 toc59 INPUT-REFERRED NOISE (DIFFERENTIAL MICROPHONE AMPLIFIER) MAX9765 toc60 DIFFERENTIAL MICROPHONE AMPLIFIER SMALL-SIGNAL TRANSIENT RESPONSE MAX9765 toc61 0 -20 -40 PSRR (dB) -60 -80 -100 -120 10 100 1k FREQUENCY (Hz) 10k VDD = 3V VDD = 5V 1000 INPUT-REFERRED NOISE (nV/Hz) AV = 20dB 100 IN 50mV/div AV = 40dB 10 OUT 50mV/div 100k 10 100 1k FREQUENCY (Hz) 10k 100k 200s/div AV = 4dB fIN = 1kHz 12 ______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux Typical Operating Characteristics (continued) (VDD = PVDD = 5V, BW = 22Hz to 22kHz, TA = +25C, unless otherwise noted.) DIFFERENTIAL MICROPHONE AMPLIFIER LARGE-SIGNAL TRANSIENT RESPONSE MAX9765 toc62 MAX9765/MAX9766/MAX9767 DIFFERENTIAL MICROPHONE AMPLIFIER OVERDRIVEN OUTPUT MAX9765 toc63 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SINGLE-ENDED INPUT) VDD = 5V MAX9765 toc64 1 IN 500mV/div IN 1V/div THD+N (%) 0.1 VOUT = 176mVRMS 0.01 OUT 1V/div OUT 1V/div 0.001 200s/div AV = 4dB fIN = 1kHz 200s/div AV = 4dB fIN = 1kHz 10 100 1k FREQUENCY (Hz) 10k 100k VOUT = 265mVRMS TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SINGLE-ENDED INPUT) MAX9765 toc65 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT AMPLITUDE (SINGLE-ENDED INPUT) MAX9765 toc66 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT AMPLITUDE (SINGLE-ENDED INPUT) VDD = 3V 10 MAX9765 toc67 1 VDD = 3V 100 VDD = 5V 10 f = 1kHz THD+N (%) 1 100 0.1 THD+N (%) VOUT = 176mVRMS THD+N (%) 1 f = 10kHz 0.1 f = 10kHz 0.1 0.01 VOUT = 265mVRMS 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.01 f = 100Hz 0.01 f = 1kHz 0.001 0 0.5 1.0 1.5 2.0 OUTPUT VOLTAGE (VRMS) 0.001 0 0.5 1.0 1.5 2.0 OUTPUT VOLTAGE (VRMS) f = 100Hz POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (SINGLE-ENDED INPUT) MAX9765 toc68 INPUT-REFERRED NOISE (SINGLE-ENDED INPUT MICROPHONE AMPLIFIER) AV = 40dB INPUT-REFERRED NOISE (nV/Hz) 500 400 300 200 100 0 MAX9765 toc69 0 -20 -40 PSRR (dB) -60 -80 -100 -120 10 100 1k FREQUENCY (Hz) 10k VDD = 3V VDD = 5V 600 100k 10 100 1k FREQUENCY (Hz) 10k 100k ______________________________________________________________________________________ 13 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 Typical Operating Characteristics (continued) (VDD = PVDD = 5V, BW = 22Hz to 22kHz, TA = +25C, unless otherwise noted.) SINGLE-ENDED MICROPHONE AMPLIFIER SMALL-SIGNAL TRANSIENT RESPONSE MAX9765 toc70 SINGLE-ENDED MICROPHONE AMPLIFIER LARGE-SIGNAL TRANSIENT RESPONSE MAX9765 toc71 IN 50mV/div IN 500mV/div OUT 100mV/div OUT 1V/div 200s/div AV = 10dB fIN = 1kHz AV = 10dB fIN = 1kHz 200s/div SINGLE-ENDED MICROPHONE AMPLIFIER OVERDRIVEN OUTPUT MAX9765 toc72 SUPPLY CURRENT vs. SUPPLY VOLTAGE (SPEAKER MODE) TA = +85C SUPPLY CURRENT (mA) MAX9765 toc73 20 IN 1V/div 16 TA = +25C 12 8 TA = -40C 4 OUT 1V/div 0 200s/div AV = 10dB fIN = 1kHz 2.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V) SUPPLY CURRENT vs. SUPPLY VOLTAGE (HEADPHONE MODE) MAX9765 toc74 SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9765 toc75 10 TA = +85C 8 SUPPLY CURRENT (mA) TA = +25C 30 25 SUPPLY CURRENT (A) 20 TA = +25C 15 10 5 0 TA = -40C TA = +85C 6 TA = -40C 4 2 0 2.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V) 2.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V) 14 ______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux Pin Description PIN MAX9765 1 2, 7, 18 MAX9766 1 2, 7, 18 MAX9767 1 2, 7, 8, 18, 23, 24, 27, 32 6 4, 21 5, 20 3 -- -- 10 11 12 13 14 15 -- -- 19 22 -- -- -- 29 -- -- -- 31 -- 16 NAME SHDN N.C. FUNCTION Active-Low Shutdown. Connect SHDN to VDD for normal operation. No Connection. Not internally connected. Left-Channel Bridged Amplifier Positive Output. OUTL+ also serves as the left-channel headphone amplifier output. Output Amplifier Power Supply. Connect PVDD to VDD. Power Ground. Connect PGND to GND. Left-Channel Bridged Amplifier Negative Output Left-Channel Input 2 Left-Channel Input 1 Differential Microphone Amplifier Noninverting Input Differential Microphone Amplifier Inverting Input Single-Ended Microphone Amplifier Input Power Supply Standby Power Supply. Connect to a standby power supply that is always on, or connect to VDD through a Schottky diode and bypass with a 220F capacitor to GND. Short to VDD if clickless operation is not essential. Microphone Bias Output. Bypass MICBIAS with a 1F capacitor to GND. Microphone Amplifier Output Right-Channel Gain Set Right-Channel Bridged Amplifier Negative Output Right-Channel Bridged Amplifier Positive Output. OUTR+ also serves as the right-channel headphone amplifier output. Address Select. A logic high sets the address LSB to 1, a logic low sets the address LSB to 0. Bidirectional Serial Data I/O Serial Clock Line Ground Right-Channel Input 2 Right-Channel Input 1 Headphone Sense Input DC Bias Bypass. See BIAS Capacitor section for capacitor selection. Connect CBIAS capacitor from BIAS to GND. Left-Channel Gain Set Microphone Amplifier Positive Output MAX9765/MAX9766/MAX9767 3 4, 21 5, 20 6 8 9 10 11 12 13 14 15 16 17 19 22 23 24 25 26, 29 27 28 30 31 32 -- 3 4, 21 5, 20 6 8 9 10 11 12 13 14 15 -- 17 -- 22 -- 24 25 26, 29 27 28 30 31 32 16 OUTL+ PVDD PGND OUTLINL2 INL1 MICIN+ MICINAUXIN VDD SVDD MICBIAS MICOUT GAINR OUTROUTR+ ADD SDA SCL GND INR2 INR1 HPS BIAS GAINL MICOUT+ ______________________________________________________________________________________ 15 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 Pin Description (continued) PIN MAX9765 -- -- -- -- -- -- -- -- MAX9766 19 23 -- -- -- -- -- -- MAX9767 17 -- 9 25 26 28 30 -- NAME MICOUTGAINM INL INT/EXT MICGAIN INR MUTE EP FUNCTION Microphone Amplifier Negative Output Mono Mode Gain Set Left-Channel Input Internal (Differential) or External (Single-Ended) Input Select. Drive INT/EXT low to select internal or high to select external microphone amplifier. Microphone Amplifier Gain Set. Tri-State Pin. Connect to VDD for gain = 10dB, float for gain = 20dB, and to GND for gain = 30dB. Right-Channel Input Mute Input Exposed Pad. Connect to ground plane of PC board to optimize heatsinking. Detailed Description The MAX9765/MAX9766/MAX9767 feature 750mW BTL speaker amplifiers, 65mW headphone amplifiers, input multiplexers, headphone sensing, differential and single-ended input microphone amplifiers, and comprehensive click-and-pop suppression. The MAX9765/ MAX9766 are controlled through an I2C-compatible, 2wire serial interface. The MAX9767 is controlled through three logic inputs: MUTE, SHDN, INT (see the Selector Guide). The MAX9765 family features exceptional PSRR (95dB at 1kHz), allowing these devices to operate from noisy digital supplies without the need for a linear regulator. The speaker amplifiers use a BTL configuration. The MAX9765/MAX9766 main amplifiers are composed of an input amplifier and an output amplifier. Resistor RIN sets the input amplifier's gain, and resistor RF sets the output amplifier's gain. The output of these two amplifiers serves as the input to a slave amplifier configured as an inverting unity-gain follower. This results in two outputs, identical in magnitude, but 180 out of phase. The overall gain of the speaker amplifiers is twice the product of the two amplifier gains (see the Gain-Setting Resistor section). A unique feature of this architecture is that there is no phase inversion from input to output. The MAX9767 does not use a two-stage input amplifier and therefore has phase inversion from input to output. When configured as a headphone (single-ended) amplifier, the slave amplifier is disabled, muting the speaker and the main amplifier drives the headphone. The MAX9765/MAX9766/MAX9767 can deliver 700mW of 16 continuous average power into a 4 load with less than 1% THD+N in speaker mode. The MAX9765/MAX9766 can deliver 70mW of continuous average power into a 16 load with less than 1% THD+N in headphone mode. The speaker amplifiers also feature thermaloverload and short-circuit current protection. All devices feature microphone amplifiers with both differential and single-ended inputs. Differential input is intended for use with internal microphones. Singleended input is intended for use with external (auxiliary) microphones. The differential input configuration is particularly effective when layout constraints force the microphone amplifier to be physically remote from the ECM microphone and/or the rest of the audio circuitry. The MAX9766/MAX9767 feature a complementary output, creating an ideal interface with CODECs and other devices with differential inputs. All devices also feature an internal microphone bias generator. Amplifier Common-Mode Bias These devices feature an internally generated common-mode bias voltage of 1.5V referenced to GND. BIAS provides both click-and-pop suppression and sets the DC bias level for the audio signal. BIAS is internally connected to the noninverting input of each speaker amplifier (see the Typical Application Circuit). Choose the value of the bypass capacitor as described in the BIAS Capacitor section. Input Multiplexer The MAX9765/MAX9766 feature a 2:1 input multiplexer on the front end of each amplifier. The multiplexer is controlled by bit 1 in the control register. A logic low ______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux which mutes the speaker amplifier and sets the device into headphone mode. 15k AUDIO INPUT MAX9765 IN_1 30k IN_2 MAX9765/MAX9766/MAX9767 Figure 1. Using the Input Multiplexer for Gain Setting selects input IN_1 and a logic high selects input IN_2. Both right- and left-channel multiplexers are controlled by the same input. The input multiplexer can also be used to further expand the number of gain options available from the MAX9765/MAX9766. Connect the audio source to the device through two different input resistors for multiple gain configurations (Figure 1). Additionally, the input multiplexer allows a speaker equalization network to be switched into the speaker signal path. This is typically useful in optimizing acoustic response from speakers with small physical dimensions. Connect HPS to the control pin of a 3-wire headphone jack as shown in Figure 2. With no headphone present, the resistive voltage-divider created by R1 and R2 sets the voltage on HPS to 44mV, setting the device to speaker mode. When a headphone plug is inserted into the jack, the control pin is disconnected from the tip contact, and HPS is pulled to VDD through R1, setting the device into headphone mode. Place a resistor in series with the control pin and HPS (R3) to prevent any audio signal from coupling into HPS when the device is in speaker mode. Shutdown The MAX9765/MAX9766/MAX9767 feature a 5A, lowpower shutdown mode that reduces quiescent current consumption and extends battery life. The drive and microphone amplifiers and the bias circuitry are disabled, the amplifier outputs (OUT_/MIC_) go high impedance, and BIAS and MICBIAS are driven to GND. The digital section of the MAX9765/MAX9766 remains active when the device is shut down through the interface. A logic high on bit 0 of the SHDN register places the MAX9765/MAX9766 in shutdown. A logic low enables the device. A logic low on the SHDN input places the devices into shutdown mode, disables the interface, and resets the I2C registers to a default state. A logic high on SHDN enables the device. A logic high on SHDN enables the devices. Mono Mode The mono MAX9766 incorporates a mixer/attenuator (see the Functional Diagram). In speaker (mono) mode, the mixer/attenuator combines the two stereo inputs (INL_ and INR_) and attenuates the resultant signal by a factor of 2. This allows for full reproduction of a stereo signal through a single speaker while maintaining optimum headroom. The resistor connected between GAINM and OUTL+ sets the device gain in speaker mode. This allows the speaker amplifier to have a different gain and feedback network from the headphone amplifier. MUTE All devices feature a mute mode. When the device is muted, the input is disconnected from the amplifiers. MUTE only affects the power amplifiers, and does not shut down the device. The MAX9765/MAX9766 MUTE mode is selected by writing to the MUTE register (see Command Byte Definitions). The left and right channels can be independently muted. The MAX9767 features an active-high MUTE input that mutes both channels. Headphone Sense Disable Input The headphone sensing function can be disabled by the HPS_D bit (MAX9765/MAX9766). HPS_D bit determines whether the device is in automatic-detection mode, or fixed-mode operation. INT/EXT The MAX9767 microphone amplifier input configuration is controlled by the INT/EXT input. A logic low In INT/EXT selects internal (differential) microphone mode. A logic high selects external (single-ended) mode. Headphone Sense Input (HPS) When the MAX9765/MAX9766 are in automatic headphone-detection mode, the state of the headphone sense input (HPS) determines the operating mode of the device. A voltage on HPS less than 0.7 VDD sets the device to speaker mode. A voltage greater than 0.9 VDD disables the inverting bridge amplifier (OUT_-), Click-and-Pop Suppression The MAX9765/MAX9766/MAX9767 feature Maxim's patented comprehensive click-and-pop suppression. During startup and shutdown, the common-mode bias voltage of the amplifiers is slowly ramped to and from the DC bias point using an S-shaped waveform. In 17 ______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 headphone mode, this waveform shapes the frequency spectrum, minimizing the amount of audible components present at the headphone. In speaker mode, the BTL amplifiers start up in the same fashion as in headphone mode. When entering shutdown, both amplifier outputs ramp to GND quickly and simultaneously. The devices can also be connected to a standby power source that ensures that the device undergoes its full shutdown cycle even after power has been removed. The value of the capacitor on the BIAS pin affects the click-and-pop energy. For optimum click/pop performance, use a 1F capacitor. Standby Power Supply (SVDD) The MAX9765/MAX9766/MAX9767 feature a patented system that provides clickless power-down when power is removed from the device. SVDD is an optional secondary supply that powers the device through its shutdown cycle when V DD is removed. During this cycle, the amplifier output DC level slowly ramps to GND, ensuring clickless power-down. If clickless power-down is required, connect SVDD to either a secondary power supply that is always on, or connect a reservoir capacitor from SVDD to GND. SVDD does not need to be connected to either a secondary power supply or reservoir capacitor for normal device operation. If click-and-pop suppression during power-down is not required, connect SVDD to VDD directly. The clickless power-down cycle only occurs when the device is in headphone mode. The speaker mode is inherently clickless, the differential architecture cancels the DC shift across the speaker. The MAX9765/ MAX9766/MAX9767 BTL outputs are pulled to GND quickly and simultaneously, resulting in no audible components. If the MAX9765/MAX9766/MAX9767 are only used as speaker amplifiers, then reservoir capacitors or secondary supplies are not necessary. When using a reservoir capacitor, a 220F capacitor provides optimum charge storage for the shutdown cycle for all conditions. If a smaller reservoir capacitor is desired, decrease the size of CBIAS. A smaller CBIAS causes the output DC level to decay at a faster rate, increasing the audible content at the speaker, but reducing the duration of the shutdown cycle. 3V R1 680k MAX9765 MAX9766 HPS OUTL+ OUTR+ R3 47k R2 10k 10k Figure 2. HPS Configuration Circuit slave-only devices, relying upon a master to generate a clock signal. The master (typically a microcontroller) initiates data transfer on the bus and generates SCL to permit that transfer. A master device communicates to the MAX9765/ MAX9766 by transmitting the proper address followed by a command and/or data words. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse. The MAX9765/MAX9766 SDA and SCL amplifiers are open-drain outputs requiring a pullup resistor to generate a logic-high voltage. Series resistors in line with SDA and SCL are optional. These series resistors protect the input stages of the devices from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). SDA and SCL idle high when the I2C bus is not busy. START and STOP Conditions When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a START condition. A START condition is a high-tolow transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 4). A START condition from the master signals the beginning of a transmission to the MAX9765/ MAX9766. The master terminates transmission by issuing the STOP condition; this frees the bus. If a REPEATED START condition is generated instead of a STOP Digital Interface The MAX9765/MAX9766 feature an I2C/SMBus-compatible 2-wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX9765/MAX9766 and the master at clock rates up to 400kHz. Figure 3 shows the 2-wire interface timing diagram. The MAX9765/MAX9766 are transmit/receive 18 ______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 SDA tSU, DAT tLOW SCL tHD, STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tHD, STA tBUF tHD, STA tSP tSU, STO Figure 3. 2-Wire Serial Interface Timing Diagram condition, the bus remains active. When a STOP condition or incorrect address is detected, the MAX9765/MAX9766 internally disconnects SCL from the serial interface until the next START condition, minimizing digital noise and feedthrough. Early STOP Conditions The MAX9765/MAX9766 recognize a STOP condition at any point during the transmission except if a STOP condition occurs in the same high pulse as a START condition (Figure 5). This condition is not a legal I2C format; at least one clock pulse must separate any START and STOP conditions. REPEATED START Conditions A REPEATED START (S r ) condition may indicate a change of data direction on the bus. Such a change occurs when a command word is required to initiate a read operation. Sr may also be used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX9765/ MAX9766 serial interface supports continuous write operations with or without an Sr condition separating them. Continuous read operations require Sr conditions because of the change in direction of data flow. Acknowledge Bit (ACK) The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data word. The receiving device always generates ACK. The MAX9765/MAX9766 generate an ACK when receiving an address or data by pulling SDA low during the ninth clock period. When transmitting data, the MAX9765/MAX9766 wait for the receiving device to generate an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a sys- S Sr P SCL SDA Figure 4. START/STOP Conditions tem fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. Slave Address The bus master initiates communication with a slave device by issuing a START condition followed by a 7-bit slave address (Figure 6). When idle, the MAX9765/ MAX9766 wait for a START condition followed by its slave address. The serial interface compares each address value bit-by-bit, allowing the interface to power down immediately if an incorrect address is detected. The LSB of the address word is the Read/Write (R/W) bit. R/W indicates whether the master is writing to or reading from the MAX9765/MAX9766 (R/W = 0 selects the write condition, R/W = 1 selects the read condition). After receiving the proper address, the MAX9765/ MAX9766 issue an ACK by pulling SDA low for one clock cycle. The MAX9765 has a factory/user-programmed address (Table 2). The MAX9766 has a factory-programmed address: 1001011. 19 ______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 Table 1. HPS Setting (MAX9765/MAX9766) SCL HPS_D BIT 0 SDA HPS 0 1 X X SPKR/ HP BIT X X 0 1 MODE BTL SE BTL SE 0 1 STOP START 1 LEGAL STOP CONDITION Table 2. I2C Slave Addresses SCL ADD CONNECTION GND VDD I2C ADDRESS 100 1000 100 1001 100 1010 100 1011 SDA SDA SCL START ILLEGAL STOP ILLEGAL EARLY STOP CONDITION Table 3. MUTE Register Format REGISTER ADDRESS BIT 7 NAME X X X MUTER MUTEL X X X VALUE Don't Care Don't Care Don't Care 0* 1 0* 1 Don't Care Don't Care Don't Care 0000 0001 DESCRIPTION -- -- -- Unmute right channel Mute right channel Unmute left channel Mute left channel -- -- -- Figure 5. Early STOP Condition S A6 A5 A4 A3 A2 A1 A0 R/W 6 5 Figure 6. Slave Address Byte Definition 4 Write Data Format There are three registers that configure the MAX9765/MAX9766: the MUTE register, SHDN register, and control register. In write data mode (R/W = 0), the register address and data byte follow the device address (Figure 7). MUTE Register The MUTE register (01hex) is a read/write register that sets the MUTE status of the device. Bit 3 (MUTEL) of the MUTE register controls the left channel, bit 4 (MUTER) controls the right channel. A logic high mutes the respective channel, a logic low brings the channel out of mute. SHDN Register The SHDN register (02hex) is a read/write register that controls the power-up state of the device. A logic high in bit 0 of the SHDN register shuts down the device; a logic low turns on the device. A logic high is required in bits 2 to 7 to reset all registers to their default register settings. 3 2 1 0 *Default state. Control Register The control register (03hex) is a read/write register that determines the device configuration. Bit 1 (IN1/IN2) controls the input multiplexer, a logic high selects input 1, a logic low selects input 2. Bit 2 (HPS_EN) controls the headphone sensing. A logic low configures the device in automatic headphone detection mode. A logic high disables the HPS input. Bit 3 (INT/EXT) controls the microphone amplifier inputs. A logic low selects differential (internal) input mode. A logic high selects single-ended (external) input mode. Bit 4 (SPKR/HP) selects the amplifier operating mode when 20 ______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 Table 4. SHDN Register Format REGISTER ADDRESS BIT 7 6 5 4 3 2 1 0 NAME RESET RESET RESET RESET RESET RESET X SHDN VALUE 0* 1 0* 1 0* 1 0* 1 0* 1 0* 1 Don't Care 0* 1 0000 0010 DESCRIPTION -- Reset device -- Reset device -- Reset device -- Reset device -- Reset device -- Reset device -- Normal operation Shutdown Table 5. Control Register Format REGISTER ADDRESS BIT 7 6 5 NAME MG2 MG1 MG0 0* 4 SPKR/HP 1 0* 3 INT/EXT 1 0* 2 HPS_D 1 0* 1 Don't Care VALUE 0000 0011 DESCRIPTION Microphone amplifier gain set; 3-bit code sets the gain of the microphone amplifiers (Table 6) Speaker mode selected Headphone mode selected Differential input selected Single-ended input selected Automatic headphone detection enabled Automatic headphone detection disabled (HPS ignored) Input 1 selected Input 2 selected -- *Default state. 1 0 IN1/IN2 X S ADDRESS 7 BITS WR ACK COMMAND 8 BITS ACK DATA 8 BITS ACK P 1 I2C SLAVE ADDRESS. SELECTS DEVICE. REGISTER ADDRESS. SELECTS REGISTER TO BE WRITTEN TO. REGISTER DATA. S ADDRESS 7 BITS WR ACK COMMAND 8 BITS ACK S ADDRESS 7 BITS WR ACK DATA 8 BITS P 1 I2C SLAVE ADDRESS. SELECTS DEVICE. REGISTER ADDRESS. SELECTS REGISTER TO BE READ. I2C SLAVE ADDRESS. SELECTS DEVICE. DATA FROM SELECTED REGISTER. Figure 7. Write/Read Data Format Example HPS_EN = 1. A logic high selects speaker mode, a logic low selects headphone mode. Bits 5 to 7 (MG0-2) control the gain of the microphone amplifiers (Table 5). Read Data Format In read mode (R/W = 1), the MAX9765/MAX9766 write the contents of the selected register to the bus. The direction of the data flow reverses following the address acknowledge by the MAX9765/MAX9766. The master device reads the contents of all registers, including the read-only status register. Table 7 shows the status register format. Figure 7 shows an example read data sequence. 21 ______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 Table 6. Microphone Gain Setting MG2 0* 0 0 0 1 1 1 1 MG1 0* 0 1 1 0 0 1 1 MG0 0* 1 0 1 0 1 0 1 MAX9765 DIFF GAIN (dB) 4 9 14 19 24 29 34 39 MAX9766 DIFF GAIN (dB) 10 15 20 25 30 35 40 45 SINGLE-ENDED GAIN (dB) 10 15 20 25 29 34 36 40 *Default state. I2C Compatibility The MAX9765/MAX9766 are compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain that pulls the data line low during the ninth clock pulse. The communication protocol supports the standard I2C 8-bit communications. The general call address is ignored. The MAX9765/MAX9766 addresses are compatible with the 7-bit I2C addressing protocol only. No 10-bit formats are supported. VRMS = VOUT(P-P) 22 2 V POUT = RMS RL Applications Information BTL Amplifiers The MAX9765/MAX9766/MAX9767 feature speaker amplifiers designed to drive a load differentially, a configuration referred to as bridge-tied load (BTL). The BTL configuration (Figure 8) offers advantages over the single-ended configuration, where one side of the load is connected to ground. Driving the load differentially doubles the output voltage compared to a singleended amplifier under similar conditions. Thus, the devices' differential gain is twice the closed-loop gain of the input amplifier. The effective gain is given by: A VD = 2 x RF RIN Since the outputs are differential, there is no net DC voltage across the load. This eliminates the need for DC-blocking capacitors required for single-ended amplifiers. These capacitors can be large, expensive, consume board space, and degrade low-frequency performance. Single-Ended Headphone Amplifier The MAX9765/MAX9766 can be configured as singleended headphone amplifiers through software or by sensing the presence of a headphone plug (HPS). In headphone mode, the inverting output of the BTL amplifier is disabled, muting the speaker. The gain is 1/2 that of the device in speaker mode, and the output power is reduced by a factor of 4. In headphone mode, the load must be capacitively coupled to the device, blocking the DC bias voltage from the load (see the Typical Application Circuit and the Output-Coupling Capacitor section). Substituting 2 x VOUT(P-P) for VOUT(P-P) into the following equations yields four times the output power due to doubling of the output voltage: Microphone Amplifiers Differential Microphone Amplifier The MAX9765/MAX9766/MAX9767 feature a low-noise, high CMRR, differential input microphone amplifier. The differential input structure is almost essential in noisy digital systems where amplification of low-amplitude analog signals is necessary such as notebooks and PDAs. When properly employed, the differential input architecture offers the following advantages: 22 ______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 Table 7. Status Register Format REGISTER ADDRESS BIT 7 6 5 4 3 2 1 0 NAME THRM AMPRAMPR+ AMPLAMPL+ HPSTS X X VALUE 0 1 0 1 0 1 0 1 0 1 0 1 Don't Care Don't Care 0000 0000 DESCRIPTION Device temperature below thermal limit Device temperature exceeding thermal limit OUTR- current below current limit OUTR- current exceeding current limit OUTR+ current below current limit OUTR+ current exceeding current limit OUTL- current below current limit OUTL- current exceeding current limit OUTL+ current below current limit OUTL+ current exceeding current limit Device in speaker mode Device in headphone mode -- -- Improved PSRR. Higher ground noise immunity. Microphone and preamplifier can be placed physically farther apart, easing PC board layout requirements. +1 VOUT(P-P) 2 x VOUT(P-P) Common-Mode Rejection Ratio Common-mode rejection ratio (CMRR) refers to an amplifier's ability to reject any signal applied equally to both inputs. In the case of amplifying a low-level microphone signal in noisy digital environments, CMRR is a key figure of merit. In audio circuits, CMRR is given by: A V CMRR(dB) = DM = INDIFF A CM VINCM where ADM is the differential gain, ACM is the commonmode gain, VINCM is the change in input commonmode voltage (IN+ and IN- connected together), and VINDIFF is the differential input voltage. Typical input voltage magnitudes are small enough such that the output is not clipped in either differential or common-mode application. The MAX9765/MAX9766/ MAX9767 differential microphone amplifier architecture CMRR actually improves as ADM increases--an additional advantage to the use of differential inputs. -1 VOUT(P-P) Figure 8. Bridge-Tied Load Configuration Power Dissipation and Heat Sinking Under normal operating conditions, the MAX9765/ MAX9766/MAX9767 can dissipate a significant amount of power. The maximum power dissipation for each package is given in the Absolute Maximum Ratings section under Continuous Power Dissipation or can be calculated by the following equation: PDISSPKG(MAX) = TJ(MAX) - TA JA where TJ(MAX) is +150C, TA is the ambient temperature, and JA is the reciprocal of the derating factor in C/W as specified in the Absolute Maximum Ratings ______________________________________________________________________________________ 23 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 section. For example, JA of the QFN package is +42C/W. The increase in power delivered by the BTL configuration directly results in an increase in internal power dissipation over the single-ended configuration. The maximum power dissipation for a given VDD and load is given by the following equation: PDISS(MAX) = 2VDD2 2RL As shown, the two-stage amplifier architecture results in a noninverting gain configuration, preserving relative phase through the MAX9765/MAX9766. The gain of the device in BTL mode is twice that of the single-ended mode. Choose RIN between 10k and 15k and RF between 15k and 100k. Input Filter The input capacitor (CIN), in conjunction with RIN, forms a highpass filter that removes the DC bias from an incoming signal. The AC-coupling capacitor allows the amplifier to bias the signal to an optimum DC level. Assuming zero-source impedance, the -3dB point of the highpass filter is given by: f-3dB = 1 2RINCIN If the power dissipation for a given application exceeds the maximum allowed for a given package, either reduce VDD, increase load impedance, decrease the ambient temperature, or add heatsinking to the device. Large output, supply, and ground PC board traces improve the maximum power dissipation in the package. Thermal-overload protection limits total power dissipation in these devices. When the junction temperature exceeds +150C, the thermal-protection circuitry disables the amplifier output stage. The amplifiers are enabled once the junction temperature cools by 8C. This results in a pulsing output under continuous thermal-overload conditions as the device heats and cools. Component Selection Gain-Setting Resistors External feedback components set the gain of the MAX9765/MAX9766/MAX9767. Resistor RIN sets the gain of the input amplifier (AVIN) and resistor RF sets the gain of the second-stage amplifier (AVOUT): 15k RF A VIN = - , A VOUT = - 15k RIN Combining AVIN and AVOUT, RIN and RF set the singleended gain of the device as follows: 15k RF RF A V = A VIN x A VOUT = - x - 15k = + R RIN IN (MAX9765 / MAX9766) R A VIN = - F RIN (MAX9767) Choose RIN according to the Gain-Setting Resistors section. Choose the CIN such that f-3dB is well below the lowest frequency of interest. Setting f-3dB too high affects the amplifier's low-frequency response. Use capacitors whose dielectrics have low-voltage coefficients, such as tantalum or aluminum electrolytic. Capacitors with high-voltage coefficients, such as ceramics, may result in an increased distortion at low frequencies. Other considerations when designing the input filter include the constraints of the overall system, the actual frequency band of interest, and click-andpop suppression. Although high-fidelity audio calls for a flat gain response between 20Hz and 20kHz, portable voice-reproduction devices such as cellular phones and two-way radios need only concentrate on the frequency range of the spoken human voice (typically 300Hz to 3.5kHz). In addition, speakers used in portable devices typically have a poor response below 150Hz. Taking these two factors into consideration, the input filter may not need to be designed for a 20Hz to 20kHz response, saving both board space and cost due to the use of smaller capacitors. 24 ______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux Output-Coupling Capacitor The MAX9765/MAX9766/MAX9767 require output-coupling capacitors to operate in single-ended (headphone) mode. The output-coupling capacitor blocks the DC component of the amplifier output, preventing DC current from flowing to the load. The output capacitor and the load impedance form a highpass filter with a -3dB point determined by: f-3dB = 1 2RLCOUT Smaller capacitor values produce faster turn-on/off times and may impact the click/pop levels. Supply Bypassing Proper power-supply bypassing ensures low-noise, low-distortion performance. Place a 0.1F ceramic capacitor from V DD to GND. Add additional bulk capacitance as required by the application. Bypass PVDD with a 100F capacitor to GND. Locate bypass capacitors as close to the device as possible. MAX9765/MAX9766/MAX9767 Layout and Grounding Good PC board layout is essential for optimizing performance. Use large traces for the power-supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance, as well as route heat away from the device. Good grounding improves audio performance, minimizes crosstalk between channels, and prevents any digital switching noise from coupling into the audio signal. If digital signal lines must cross over or under audio signal lines, ensure that they cross perpendicular to each other. The MAX9765/MAX9766/MAX9767 thin QFN packages feature exposed thermal pads on their undersides. This pad lowers the package's thermal resistance by providing a direct heat conduction path from the die to the printed circuit board. Connect the pad to signal ground by using a large pad, or multiple vias to the ground plane. As with the input capacitor, choose COUT such that f-3dB is well below the lowest frequency of interest. Setting f-3dB too high affects the amplifier`s low-frequency response. Load impedance is a concern when choosing COUT. Load impedance can vary, changing the -3dB point of the output filter. A lower impedance increases the corner frequency, degrading low-frequency response. Select COUT such that the worst-case load/COUT combination yields an adequate response. Select capacitors with low ESR. BIAS Capacitor BIAS is the output of the internally generated 1.5VDC bias voltage. The BIAS bypass capacitor, C BIAS , improves PSRR and THD+N by reducing power supply and other noise sources at the common-mode bias node, and also generates the clickless/popless, startup/shutdown DC bias waveforms for the speaker amplifiers. Bypass BIAS with a 1F capacitor to GND. ______________________________________________________________________________________ 25 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 Typical Application Circuit 0.1F VDD BIAS SVDD 1F *CSVDD PVDD 15k GAINL 0.47F 15k INL1 OUTL0.47F 15k OUTL+ 220F HPF CODEC INL2 MAX9765 0.47F 15k INR1 OUTR0.47F 15k HPF INR2 OUTR+ GAINR 15k 220F SCL MICROCONTROLLER SDA ADD SHDN HPS 0.1F AUX_IN 2.2k MICOUT MICBIAS 2.2k 0.1F IN+ IN0.1F *CSVDD IS ONLY REQUIRED IF LOW CLICK-AND-POP LEVELS ARE NECESSARY DURING POWER-DOWN. 26 ______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux Functional Diagrams VDD MAX9765/MAX9766/MAX9767 0.1F * CSVDD PVDD VDD 15k SVDD GAINL AUDIO INPUT AUDIO INPUT 0.47F 15k VDD 15k 680k INL1 INL2 2:1 INPUT MUX 15k OUTL+ 0.47F 15k 220F BIAS 1F 15k BIAS 15k OUTL- 15k 0.47F AUDIO INPUT AUDIO INPUT 0.47F GAINR 15k INR1 INR2 15k 220F 15k SHDN SCL SDA ADD 0.1F AUXIN 10k HPS HPS I2C LOGIC 15k OUTR47k 2:1 INPUT MUX 15k OUTR+ 15k 2.2k MICBIAS 0.1F 2.2k 0.1F MICIN+ MICIN0.1F GND MIC BIAS 2:1 OUTPUT MUX MICOUT MAX9765 *CSVDD IS ONLY REQUIRED IF LOW CLICK-AND-POP LEVELS ARE NECESSARY DURING POWER-DOWN. ______________________________________________________________________________________ 27 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 Functional Diagrams (continued) VDD 0.1F PVDD VDD SVDD 15k AUDIO INPUT AUDIO INPUT 0.47F 0.47F 15k GAIN MUX INL1 INL2 15k 220F BIAS 1F 15k OUTL2:1 INPUT MUX 15k OUTL+ GAINL GAINM VDD 15k 15k 680k * CSVDD BIAS 15k 15k AUDIO INPUT AUDIO INPUT 0.47F 0.47F 15k GAINR INR1 INR2 2:1 INPUT MUX 15k OUTR 15k 15k SHDN SCL 220F 0.1F SDA AUXIN I2C LOGIC MAX9766 HPS HPS 47k 10k 2.2k MICBIAS 0.1F 2.2k 0.1F MICIN+ MICIN0.1F GND MIC BIAS 2:1 OUTPUT MUX MICOUT+ MICOUT- *CSVDD IS ONLY REQUIRED IF LOW CLICK-AND-POP LEVELS ARE NECESSARY DURING POWER-DOWN. 28 ______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux Functional Diagrams (continued) MAX9765/MAX9766/MAX9767 15k 15k AUDIO INPUT 0.1F 15k INL OUTL+ 15k VDD 0.1F VDD PVDD 15k OUTL- BIAS 0.1F OUTR+ SHDN 15k MUTE INTEXT 0.47F 15k INR 15k OUTR+ AUDIO INPUT 0.1F AUXIN MAX9767 2.2k MICBIAS 1F 2.2k 0.1F MICIN+ MICIN0.1F GADJ GAIN CONTROL MIC BIAS MICOUT+ OUTPUT MUX MICOUT- GND PGND ______________________________________________________________________________________ 29 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 Pin Configurations GAINL GAINL BIAS INR1 INR2 GND GND BIAS INR1 INR2 GND GND 26 HPS SCL HPS SCL 25 24 SDA 23 GAINM 22 OUTR+ 21 PVDD 20 PGND 19 MICOUT18 N.C. 17 GAINR 9 INL1 10 MICIN+ 11 MICIN12 AUXIN 13 VDD 14 SVDD 15 MICBIAS 16 MICOUT+ 32 SHDN N.C. OUTL+ PVDD PGND OUTLN.C. INL2 1 2 3 4 5 6 7 8 9 INL1 31 30 29 28 27 26 25 24 SDA 23 ADD 22 OUTR+ 21 PVDD SHDN N.C. OUTL+ PVDD PGND OUTLN.C. INL2 1 2 3 4 5 6 7 8 32 31 30 29 28 27 MAX9765 20 PGND 19 OUTR18 N.C. 17 GAINR MAX9766 10 MICIN+ 11 MICIN- 12 AUXIN 13 VDD 14 SVDD 15 MICBIAS 16 MICOUT THIN QFN THIN QFN MICGAIN 26 32 SHDN N.C. OUTLPVDD PGND OUTL+ N.C. N.C. 1 2 3 4 5 6 7 8 9 INL 31 30 29 28 27 25 24 N.C. 23 N.C. 22 OUTR+ 21 PVDD MAX9767 INT/EXT 20 PGND 19 OUTR18 N.C. 17 MICOUT16 MICOUT+ MUTE BIAS GND N.C. 10 MICIN+ 11 MICIN- 12 AUXIN 13 VDD N.C. 14 SVDD INR 15 MICBIAS THIN QFN 30 ______________________________________________________________________________________ 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux Selector Guide PART MAX9765 MAX9766 MAX9767 CONTROL INTERFACE I2C compatible I2C compatible Parallel SPEAKER AMPLIFIER Stereo Mono Stereo INPUT MULTIPLEXER -- HEADPHONE AMPLIFIER Stereo Stereo -- MICROPHONE AMPLIFIER OUTPUT Single ended Differential Differential MAX9765/MAX9766/MAX9767 Chip Information MAX9765 TRANSISTOR COUNT: 4829 MAX9766 TRANSISTOR COUNT: 4533 MAX9767 TRANSISTOR COUNT: 4731 PROCESS: BiCMOS ______________________________________________________________________________________ 31 750mW Audio Amplifiers with Headphone Amp, Microphone Preamp, and Input Mux MAX9765/MAX9766/MAX9767 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QFN THIN.EPS L D2 D D/2 MARKING k L E/2 E2/2 E (NE-1) X e C L C L b D2/2 0.10 M C A B XXXXX E2 PIN # 1 I.D. DETAIL A e (ND-1) X e PIN # 1 I.D. 0.35x45 DETAIL B e L1 L C L C L L e 0.10 C A 0.08 C e C A1 A3 PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm -DRAWING NOT TO SCALE- 21-0140 G 1 2 COMMON DIMENSIONS PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 A3 b D E e k L L1 N ND NE JEDEC 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. PKG. CODES T1655-1 T1655-2 T1655N-1 T2055-2 T2055-3 T2055-4 T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1 EXPOSED PAD VARIATIONS D2 MIN. NOM. MAX. MIN. E2 NOM. MAX. L 0.15 DOWN BONDS ALLOWED 3.00 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.25 - 0.25 - 0.25 - 0.25 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 16 4 4 WHHB 20 5 5 WHHC 28 7 7 WHHD-1 32 8 8 WHHD-2 - ** ** ** ** ** ** 0.40 ** ** ** ** ** ** ** 0.40 ** ** ** ** ** NO YES NO NO YES NO Y NO NO YES YES NO NO YES Y N NO YES NO NO NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. ** SEE COMMON DIMENSIONS TABLE 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm -DRAWING NOT TO SCALE- 21-0140 G 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________32 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. |
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